usbcore.cpu package

Submodules

usbcore.cpu.dummyusb module

class usbcore.cpu.dummyusb.DummyUsb(iobuf, debug=False, vid=4617, pid=23536, product='Fomu Bridge', manufacturer='Foosn')

Bases: migen.fhdl.module.Module

Implements a device that simply responds to the most common SETUP packets. It is intended to be used alongside the Wishbone debug bridge.

usbcore.cpu.epfifo module

class usbcore.cpu.epfifo.Endpoint

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

class usbcore.cpu.epfifo.EndpointIn

Bases: usbcore.cpu.epfifo.Endpoint

Endpoint for Device->Host data.

Reads from the buffer memory. Raises packet IRQ when packet has been sent. CPU writes to the head CSR to push data onto the FIFO.

class usbcore.cpu.epfifo.EndpointNone

Bases: migen.fhdl.module.Module

class usbcore.cpu.epfifo.EndpointOut

Bases: usbcore.cpu.epfifo.Endpoint

Endpoint for Host->Device data.

Raises packet IRQ when new packet has arrived. CPU reads from the head CSR to get front data from FIFO. CPU writes to head CSR to advance the FIFO by one.

class usbcore.cpu.epfifo.FakeFifo

Bases: migen.fhdl.module.Module

class usbcore.cpu.epfifo.PerEndpointFifoInterface(iobuf, endpoints=[<EndpointType.BIDIR: 3>, <EndpointType.IN: 1>, <EndpointType.BIDIR: 3>], debug=False)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Implements a CPU interface with each endpoint having it’s own FIFO.

Each endpoint has;

• A FIFO with one end connected to CSRs and the other to the USB core.
• Control bits.
• A pending flag.

An output FIFO is written to using CSR registers. An input FIFO is read using CSR registers.

Extra CSR registers set the response type (ACK/NAK/STALL).

usbcore.cpu.epfifo_test module

class usbcore.cpu.epfifo_test.TestPerEndpointFifoInterface(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase, usbcore.test.common.CommonUsbTestCase, usbcore.test.clock.CommonTestMultiClockDomain, unittest.case.TestCase

clear_pending(epaddr)

dtb(epaddr)

expect_data(epaddr, data)

Expect that an endpoints buffer has given contents.

expect_last_tok(epaddr, value)

get_endpoint(epaddr)

maxDiff = None

on_usb_12_edge()

on_usb_48_edge()

pending(epaddr)

response(epaddr)

run_sim(stim)

setUp()

Hook method for setting up the test fixture before exercising it.

set_data(epaddr, data)

Set an endpoints buffer to given data to be sent.

set_response(epaddr, v)

tick_sys()

tick_usb12()

tick_usb48()

trigger(epaddr)

update_internal_signals()

usbcore.cpu.epmem module

class usbcore.cpu.epmem.MemInterface(iobuf, num_endpoints=3, depth=512)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Interfaces the USB state machine core to the soft CPU.

This interface has two memory regions:

• Output memory. Writable by CPU, readable by USB Core.
• Input memory. Writable by USB Core, readable by CPU.

Each endpoint has:

• A current pointer
• A current length
• Control bits
• A pending flag

Pointers are all relative to the start of the memory.

On output endpoints, both the pointer and length are read only. On input endpoints, the pointer and length are writable.

To accept / send data from an endpoint you set the arm bit. The USB core will then respond to the next request and update the pointer / length.

After a packet has been sent or received, the pending flag will be raised. While the pending flag is raised, the USB core will respond with NAK.

The arm, dtb, and sta registers are bitmasks. They are packed in pairs of IO. If you only have one endpoint, then arm, dtb, and sta are packed like this:

IO

Where

Bit 1 is set to affect EP0 IN, and Bit 0 is set to affect EP0 OUT

Likewise, if you have 3 endpoints, they are packed as:

IOIOIO |||||- EP0 OUT ||||– EP0 IN |||— EP1 OUT ||—- EP1 IN |—– EP2 OUT —— EP2 IN

Therefore, to ARM the EP1 IN endpoint, do:

arm_write((1<<1) | 1);

Or for EP2 IN:

arm_write((1<<2) | 1);

csr_bits(csr)

Work around the lack of bit-addressability in CSRs by creating an array of signals that are aliases of the various CSR storage values.

usbcore.cpu.epmem_test module

class usbcore.cpu.epmem_test.TestMemInterface(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase, usbcore.test.common.CommonUsbTestCase, usbcore.test.clock.CommonTestMultiClockDomain, unittest.case.TestCase

arm(epaddr)

clear_arm(epaddr)

clear_dtb(epaddr)

clear_pending(epaddr)

clear_sta(epaddr)

dtb(epaddr)

expect_data(epaddr, data)

Expect that an endpoints buffer has given contents.

format_epaddr(ep)

get_evsrc(epaddr)

get_len_csr(epaddr)

get_module(epaddr, name, obj=None)

get_ptr_csr(epaddr)

maxDiff = None

on_usb_12_edge()

on_usb_48_edge()

pending(epaddr)

response(epaddr)

run_sim(stim)

setUp()

Hook method for setting up the test fixture before exercising it.

set_arm(epaddr)

set_csr(csr, epaddr, v)

set_data(epaddr, data)

Set an endpoints buffer to given data to be sent.

set_dtb(epaddr)

set_response(epaddr, v)

set_sta(epaddr)

sta(epaddr)

tick_sys()

tick_usb12()

tick_usb48()

trigger(epaddr)

update_internal_signals()

usbcore.cpu.eptri module

class usbcore.cpu.eptri.InHandler(usb_core)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Endpoint for Device->Host data.

Reads from the buffer memory. Raises packet IRQ when packet has been sent. CPU writes to the head CSR to push data onto the FIFO.

class usbcore.cpu.eptri.OutHandler(usb_core)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

class usbcore.cpu.eptri.SetupHandler(usb_core)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Handle SETUP packets.

SETUP packets must always respond with ACK. Sometimes, they are followed by DATA packets, but not always.

data

Data from the last SETUP packet. It will be 10 bytes long, because it will include the CRC16. This is a FIFO; use DATA_ACK to advance the queue.

data CSR Interface

Type:CSR

status

Status about the most recent SETUP packet, and the state of the FIFO.

status CSR Interface

Type:CSRStatus

ctrl

Controls for managing SETUP packets.

CTRL CSR Interface

Type:CSRStorage

class usbcore.cpu.eptri.TriEndpointInterface(iobuf, debug=False)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Implements a CPU interface with three endpoints:

• SETUP
• EPIN
• EPOUT

Each endpoint has:

• A FIFO with one end connected to CSRs and the other to the USB core.
• Control bits.
• A pending flag.

An output FIFO is written to using CSR registers. An input FIFO is read using CSR registers.

Extra CSR registers set the response type (ACK/NAK/STALL).

usbcore.cpu.eptri_test module

class usbcore.cpu.eptri_test.TestTriEndpointInterface(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase, usbcore.test.common.CommonUsbTestCase, usbcore.test.clock.CommonTestMultiClockDomain, unittest.case.TestCase

clear_pending(epaddr)

dtb(epaddr)

expect_data(epaddr, data)

Expect that an endpoints buffer has given contents.

expect_last_tok(epaddr, value)

expect_setup(epaddr, data)

maxDiff = None

on_usb_12_edge()

on_usb_48_edge()

pending(epaddr)

response(epaddr)

run_sim(stim)

setUp()

Hook method for setting up the test fixture before exercising it.

set_data(epaddr, data)

Set an endpoints buffer to given data to be sent.

set_response(epaddr, v)

tick_sys()

tick_usb12()

tick_usb48()

trigger(epaddr)

update_internal_signals()

usbcore.cpu.unififo module

class usbcore.cpu.unififo.UsbUniFifo(iobuf)

Bases: migen.fhdl.module.Module, litex.soc.interconnect.csr.AutoCSR

Presents the USB data stream as two FIFOs via CSR registers.

usbcore.cpu.unififo_test module

class usbcore.cpu.unififo_test.TestUsbUniFifo(methodName='runTest')

Bases: usbcore.test.common.BaseUsbTestCase, usbcore.test.common.CommonUsbTestCase, usbcore.test.clock.CommonTestMultiClockDomain, unittest.case.TestCase

clear_pending(epaddr)

dtb(epaddr)

expect_data(epaddr, data)

Expect that an endpoints buffer has given contents.

maxDiff = None

next_state(state)

on_usb_12_edge()

on_usb_48_edge()

pending(epaddr)

recv_packet()

response(epaddr)

run_sim(stim)

send_packet(pid, data=None)

setUp()

Hook method for setting up the test fixture before exercising it.

set_data(epaddr, data)

Set an endpoints buffer to given data to be sent.

set_response(epaddr, v)

tick_sys()

tick_usb12()

tick_usb48()

trigger(epaddr)

update_internal_signals()

usbcore.cpu.usbwishbonebridge module

class usbcore.cpu.usbwishbonebridge.USBWishboneBridge(usb_core, clk_freq=12000000, magic_packet=67)

Bases: migen.fhdl.module.Module

Module contents